In recent years, as a package structure suitable for a superior performance and a sophisticated function of a semiconductor device, the SiP (System in Package) structure is well known. According to the SiP structure, a system is built by laminating a plurality of semiconductor elements such as a CPU (central processing unit), a memory or the like, and by mounting the laminated semiconductor elements on a package. Moreover, according to the SiP structure, it has been progressed in recent years to make pins further increasing and to make a pitch between electrodes finer in order to improve capability of transferring data between the semiconductor elements.
FIGS. 9A and 9B show an example of a method for manufacturing a semiconductor device according to a related art.
Firstly, two semiconductor devices 1101 are arranged so as to be opposed to each other. For each semiconductor device 1101, a solder bump 15, whose main constituent is tin (Sn), is formed on an electrode 2 of a semiconductor element 1 through a barrier metal 14. Or, a thin film made of gold (Au) may be formed on the barrier metal 14 of one of the semiconductor elements 1 (FIG. 9A). Afterward, the solder bumps 15 existing at the corresponding positions are touched each other, then heated, and pressed. As a result, the solder bumps react, and are connected to each other. Finally, underfill resin having thermal hardening properties is filled between two semiconductor elements 1. The underfill resin changes to a bonding resin layer 7 in the hardening process. Through carrying out the above-mentioned processes, a circuit device 1201 is obtained (FIG. 9B).
In order to improve the productivity, Japanese Patent Application Laid-Open No. 2007-142232 (patent document 1) discloses a manufacturing method to mount a semiconductor element after making liquid resin flow on the substrate side, and then to connect electrodes to each other and to carry out a thermal hardening process for the resin.
Japanese Patent Application Laid-Open No. 2005-294430 (patent document 2) discloses a manufacturing method to supply resin before mounting a semiconductor element. Specifically, the patent document 2 discloses a manufacturing method to form a bonding resin layer, which is in a semi hard state, on the semiconductor element side, and to make the surface of a solder bump exposed from the bonding resin layer through grinding the solder bump and the bonding resin layer afterward and to make a surface of the semiconductor element flat.
Japanese Patent Application Laid-Open No. 2004-172491 (patent document 3) discloses structure wherein a surface of a projecting electrode and a surface of a stopper mask layer are made flush. Moreover, the patent document 3 discloses that thermoplastic resin or low softening point (melting point) glass, which has adhesive properties, is applied to the stopper mask layer.